I. AUTHORS 1. Adrian Stoica Jet Propulsion Laboratory, 4,800 Oak Grove Dr. 303-300 91109 Pasadena CA e-mail: Adrian.stoica@jpl.nasa.gov Telephone: (818) 354-2190 2. Ricardo Zebulum Jet Propulsion Laboratory, 4,800 Oak Grove Dr. 303-300 91109 Pasadena CA e-mail: ricardo.zebulum@jpl.nasa.gov Telephone: (818) 354-7623 3. Didier Keymeulen Jet Propulsion Laboratory, 4,800 Oak Grove Dr. 303-300 91109 Pasadena CA e-mail: didier.keymeulen@jpl.nasa.gov e-mail: adrian.stoica.jpl.nasa.gov Telephone: (818) 354-4280 4. Michael Ian Ferguson Jet Propulsion Laboratory, 4,800 Oak Grove Dr. 303-300 91109 Pasadena CA e-mail: fergie@ehw.jpl.nasa.gov Telephone: (818) 393-6967 5. Vu Duong Jet Propulsion Laboratory, 4,800 Oak Grove Dr. 303-300 91109 Pasadena CA e-mail: vu.a.duong@jpl.nasa.gov Telephone: (818) 354-2190 6. Xin Guo Chromatech e-mail: guo@chromatec.us II) Paper Title Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration III) Abstract Current techniques in evolutionary synthesis of analog and digital circuits designed at transistor level have focused on achieving desired functional response, without sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. This paper argues that moving from evolutionary ‘design-for experimentation’ to ‘design-for-implementation’ requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to provide great use to evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here for illustration is a multi-function NAND/NOR logic gate circuit, for which evolution obtained a creative novel topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5-micron CMOS technology and silicon tests showed good correspondence with the simulations. IV) Statement A and D (A) … or would qualify today as a patentable new invention. (D) The result is publishable in its own rights a new scientific result ¾ independent of the fact that was mechanically created. The evolved circuit would qualify as a patentable new invention (A) (it is currently published and protected as a NTR). The circuit performs NAND and NOR logic functions according to the value of the power supply value (Vdd). Evolution obtained a creative novel topology more compact than what has been achieved by multiplexing a NAND and a NOR gate (conventional solution using a standard digital library). Although there are conventional approaches for multi-functional logic gates controlled by an external voltage signal, no conventional design is available with the logic function controlled by Vdd. Such NAND/NOR designs can be used for example in programmable logic cells, or in processor design in maximizing the flexibility of using spare gates for correcting design errors through changes in the interconnection of logic elements. This design task would be a complex task to be carried out by a circuit designer, particularly with the constraint of using 6 transistors (as the proposed design) or less. Therefore the author believe that criteria D is also satisfied. Both the circuit topology and the transistor sizes were automatically synthesized from scratch by artificial evolution. The circuit was fabricated in a 0.5-micron CMOS technology and silicon tests showed good correspondence with the simulations. New methods were used to ensure that the evolved solution cover the intended operational space. These techniques proved useful in obtaining a circuit that worked as predicted in silicon. VI) To be published in the IEE computing/digital techniques journal on evolvable hardware. To be published in 2004. Andy Tyrrell (editor), London, England.