------------------------------------------------------------------------------------------------------------------- 1. the complete title of the publication; Macro Placement by Wire-Mask-Guided Black-Box Optimization ------------------------------------------------------------------------------------------------------------------- 2. the authors' information; Yunqi Shi; School of Artificial Intelligence, Nanjing University; 163 Xianlin Avenue, Nanjing, Jiangsu, China, 210023; shiyq@lamda.nju.edu.cn; +86-18068871915 Ke Xue; School of Artificial Intelligence, Nanjing University; 163 Xianlin Avenue, Nanjing, Jiangsu, China, 210023; xuek@lamda.nju.edu.cn; +86-15800040583 Lei Song; School of Artificial Intelligence, Nanjing University; 163 Xianlin Avenue, Nanjing, Jiangsu, China, 210023; songl@lamda.nju.edu.cn; +86-13382403635 Chao Qian; School of Artificial Intelligence, Nanjing University; 163 Xianlin Avenue, Nanjing, Jiangsu, China, 210023; qianc@lamda.nju.edu.cn; +86-13805195004 ------------------------------------------------------------------------------------------------------------------- 3. the name of the corresponding author; Chao Qian qianc@lamda.nju.edu.cn ------------------------------------------------------------------------------------------------------------------- 4. the abstract of the paper; The development of very large-scale integration (VLSI) technology has posed new challenges for electronic design automation (EDA) techniques in chip floorplanning. During this process, macro placement is an important subproblem, which tries to determine the positions of all macros with the aim of minimizing half-perimeter wirelength (HPWL) and avoiding overlapping. Previous methods include packing-based, analytical and reinforcement learning methods. In this paper, we propose a new black-box optimization (BBO) framework (called WireMask-BBO) for macro placement, by using a wire-mask-guided greedy procedure for objective evaluation. Equipped with different BBO algorithms, WireMask-BBO empirically achieves significant improvements over previous methods, i.e., achieves significantly shorter HPWL by using much less time. Furthermore, it can fine-tune existing placements by treating them as initial solutions, which can bring up to 50% improvement in HPWL. WireMask-BBO has the potential to significantly improve the quality and efficiency of chip floorplanning, which makes it appealing to researchers and practitioners in EDA and will also promote the application of BBO. Our code is available at https://github.com/lamda-bbo/WireMask-BBO. ------------------------------------------------------------------------------------------------------------------- 5. a list containing one or more of the eight letters (A, B, C, D, E, F, G, or H); B, D, E, F ------------------------------------------------------------------------------------------------------------------- 6. a statement stating why the result satisfies the criteria that the contestant claims (see examples of statements of human-competitiveness as a guide to aid in constructing this part of the submission); Our submission specifically targets the problem of macro placement within the field of Electronic Design Automation (EDA). This process involves positioning large components, such as RAMs and ROMs, on a chip canvas—a critical step in EDA. Despite decades of research, full automation in macro placement has remained elusive. Existing automated solutions generate placements quickly but often fall short of the required quality, necessitating several iterations by physical designers. This manual refinement process is time-consuming, typically requiring 2 to 4 weeks for circuits with more than 200 macros to achieve the desired floorplan quality. Given that decisions made during the macro placement stage significantly affect the timing and power efficiency of the chip, enhancements in the quality of automated placements can substantially reduce the overall design turnaround time. Below, we describe how our results satisfy the criteria we claim: (B) Superior to Established Methods: Our results surpass those of the state-of-the-art methods, specifically MaskPlace [1] and ChiPFormer [2], as detailed in Table 1 and 11 of our paper. Compared to MarkPlace (which trains a reinforcement learning (RL) agent to sequentially determine each macro's location) [1], our method WireMask-EA (i.e., WireMask-BBO equipped with an evolutionary algorithm) achieves an average improvement of 40% in the wirelength metric. Compared to ChipFormer (which employs a transformer to improve the RL agent's generalization ability) [2], our method achieves better wirelength on all 10 compared chip cases consuming the same number of evaluations. These improvements demonstrate a significant advancement over previously accepted scientific results in the field of EDA. (D) Publishable as a Novel Scientific Result: Macro placement is a crucial issue in EDA, and any advancements, whether achieved by human or machine, are rapidly adopted in the industry. Therefore, our results are undeniably publishable as a new scientific result, independent of their mechanical origin. (E) Comparable or Superior to Recent Human-Created Solutions: ChiPFormer [2], one of our baseline methodologies, consistently and significantly surpasses the performance of solutions crafted by human experts across all 6 industry chip cases, achieving an average improvement of 30% in key PPA (power, performance, and area) metrics, as detailed in its Table 4. Our results improve upon those of ChiPFormer on all 10 open chip cases, indicating that they are at least equal to, if not better than, the most recent human-created solutions in macro placement. The ongoing effort by human experts to enhance macro placement results also highlights the significance of our method and results. (F) Achievement in the Field: Our methodology significantly outperforms another baseline, Graph Placement [3], which initially demonstrates the effectiveness of RL for the macro placement problem and was published in the prestigious journal Nature by Google in 2021. Compared to Graph Placement [3], WireMask-EA achieves an average improvement of 70% on wirelength. This demonstrates that our results not only advance the field but can also be considered a new achievement within it. The excellent performance of WireMask-EA also demonstrates the potential of evolutionary algorithms for EDA. [1] Yao Lai, Yao Mu, and Ping Luo. Maskplace: Fast chip placement via reinforced visual representation learning. In Advances in Neural Information Processing Systems 35 (NeurIPS'22), pages 24019-24030, New Orleans, LA, 2022. [2] Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang, Jianye Hao, and Ping Luo. Chipformer: Transferable chip placement via offline decision transformer. In Proceedings of the 40th International Conference on Machine Learning (ICML'23), pages 18346–18364, Honolulu, HA, 2023. [3] Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, et al. A graph placement methodology for fast chip design. Nature, 594(7862):207–212, 2021. ------------------------------------------------------------------------------------------------------------------- 7. a full citation of the paper; Yunqi Shi, Ke Xue, Lei Song, and Chao Qian. Macro Placement by Wire-Mask-Guided Black-Box Optimization. In Advances in Neural Information Processing Systems 36 (NeurIPS'23), pages 6825-6843, New Orleans, LA, 2023. ------------------------------------------------------------------------------------------------------------------- 8. a statement as to how the prize money, if any, is to be divided among the co-authors; The prize money is to be divided equally among the 4 co-authors. ------------------------------------------------------------------------------------------------------------------- 9. a statement stating why the authors expect that their entry would be the "best"; Our method addresses the critical challenge of macro placement by introducing an efficient framework, WireMask-BBO, alongside a targeted genetic algorithm, which we describe as an "evolutionary algorithm" in our paper. This approach not only tackles the problem effectively but also reaffirms the power of evolutionary computation within the EDA community . What's more important, it achieves human-quality results that are practical for real-world application, marking a notable advancement in macro placement strategies. For the communities focused on black-box optimization and evolutionary computation, our work highlights the macro placement challenge as a crucial problem. By doing so, we motivate the development and adoption of more problem-specific evolutionary computation methods, collectively advancing the field. Furthermore, we have made our code openly available [1] and provided detailed instructions for reproducing our results. This transparency has fostered further innovation, leading to enhanced solutions that have garnered recognition and acceptance at ICML 2024 [2]. This cycle of ongoing improvement and community engagement strongly positions our entry as a leading contender in the field. [1] https://github.com/lamda-bbo/WireMask-BBO [2] Zijie Geng, et al. Reinforcement Learning within Tree Search for Fast Macro Placement. In Proceedings of the 41st International Conference on Machine Learning (ICML'24), Vienna, Austria, 2024, to appear. ------------------------------------------------------------------------------------------------------------------- 10. An indication of the general type of genetic or evolutionary computation used; GA (genetic algorithms) ------------------------------------------------------------------------------------------------------------------- 11. The date of publication of the paper. Dec 10-16 2023, NeurIPS 2023 -------------------------------------------------------------------------------------------------------------------